The present invention is directed, in general, to microprocessors and, more specifically, to microprocessors that implement associative data arrays, including cache memory circuits.
The start-up (or xe2x80x9cbootxe2x80x9d) operations that occur when a computer is first started (or is restarted) include a number of built-in self-test (BIST) routines that are run on different components of the computer in order to validate the operation of the computer. If all component parts xe2x80x9cpassxe2x80x9d the BIST routines, the computer begins running applications selected by the user. If one or more components xe2x80x9cfailxe2x80x9d the BIST routine(s) and the error(s) is (are) catastrophic in nature, the computer may completely shut down, thereby becoming completely inoperable. If a less-than-catastrophic error occurs, the computer may perform a xe2x80x9cpatchxe2x80x9d operation that allows the computer to continue to operate, albeit in a mode that is somewhat degraded. For example, if a self test routine determines that a memory location in RAM is bad, the operating system can xe2x80x9cmap outxe2x80x9d the bad RAM location, including perhaps surrounding memory locations, and continue to operate. Thereafter, the computer will not read or write to the memory location(s) that were mapped out as a result of the self-test failure.
BIST routines are implemented in a wide variety of processing circuitry, including microprocessors and digital signal processors. The BIST routines may be performed by BIST circuitry integrated into the same chip as the processing circuitry, or may be performed by external BIST circuitry that is implemented on the same circuit board as the processing circuitry. Complex devices, such as microprocessors, frequently include several on-board BIST circuits that test and validate different sub-components of the device.
Many processing circuits contain what are known as xe2x80x9cN-way set associativexe2x80x9d data arrays. For example, in the x86 family of processors, including Cyrix 6x86MX processors, AMD 5k86 processors, and Intel Pentium processors, one or more of the L1 cache, L2 cache, L1 translation look-aside buffer (TLB), and/or L2 TLB are typically implemented as N-way set associative data arrays. Therefore, one or more BIST circuits may be implemented in such microprocessors to test and validate the N-way set associative data arrays.
Like any other device that is integrated into a processing device, a BIST circuit occupies space on the integrated circuit wafer, it consumes power, and it may itself cause a failure. Thus, a BIST circuit integrated into, for example, a microprocessor is preferably a relatively simple device having a minimum number of transistors. Unfortunately, many of the microprocessors found in the prior art use separate BIST circuits for testing each cache and TLB. Furthermore, these prior art BIST circuits are frequently relatively large, microcode-driven devices that run a series of data patterns through an individual data array. The net result is that a large amount of BIST circuitry is used in the prior art processing devices.
Therefore, there is a need in the art for improved BIST devices for testing and validating components in a processing device. In particular, there is a need for improved microprocessors containing comparatively simple BIST circuits capable of testing N-way set associative data arrays in the microprocessor. More particularly, there is a need in the art for improved microprocessors containing a multifunction BIST circuit capable of testing more than one of the N-way set associative data arrays in a microprocessor.
To address the above-discussed deficiencies of the prior art, the present invention provides a circuit and method for testing an N-way set associative data array in a processing device. The circuit and method implement a xe2x80x9cbootstrapxe2x80x9d strategy for testing the ways of the data array. A control circuit copies a small test program into a first portion of one way of the data array. The test program comprises assembly language code executable by the processing device. Next, the control circuit compares the values of the copied test program with the original test program to determine whether the first portion of the first way properly stored the copied test program. If the first portion of the first way passes this test, the processing device then executes the assembly language test program in order to validate the remaining portion of the first way, and all of each remaining way.
Accordingly, one embodiment of the present invention presents, for use in a processing device having an N-way set associative data array, a built-in self-test (BIST) circuit for testing the validity of storage locations in the data array, the BIST circuit comprising: 1) a memory capable of storing a test program executable by the processing device, wherein the test program is capable of testing the validity of the storage locations in the data array; and 2) a controller capable of copying the test program from the memory into first selected storage locations in a first way in the data array, wherein the processing device executes the copied test program stored in the first selected storage locations subsequent to the copying to thereby test the validity of second selected storage locations in at least one of the N ways.
In another embodiment of the present invention, the second selected storage locations and the first selected storage locations are disposed in the same way.
In another embodiment of the present invention, the second selected storage locations and the first selected storage locations are disposed in different ways.
In still another embodiment of the present invention, the controller retrieves at least a portion of the copied test program from the first selected storage locations and compares the retrieved portion to a corresponding portion of the test program in the memory to determine if the retrieved portion and the corresponding portion are identical.
In yet another embodiment of the present invention, the controller, in response to a determination that the retrieved portion and the corresponding portion are not identical, copies the test program from the memory into third selected storage locations in a second way in the data array.
In a further embodiment of the present invention, the controller retrieves at least a portion of the copied test program from the third selected storage locations and compares the retrieved portion to a corresponding portion of the test program in the memory to determine if the retrieved portion and the corresponding portion are identical.
In a still further embodiment of the present invention, the processing device executes the copied test program stored in the third selected storage locations subsequent to the copying to thereby test the validity of second selected storage locations in at least one of the N ways.
In another embodiment of the present invention, the memory is a read-only memory (ROM).
In another embodiment of the present invention, the data array is a cache memory in the processing device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.